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summit microelectronics, inc. ? 300 orchard city drive, suite 131 campbell, ca 95008 telephone 408-378- 6461 fax 408-378-6586 www.summitmicro.com 1 characteristics subject to change without notice ? summit microelectronics, inc. 2000 2036 5.0 4/18/00 summit microelectronics , inc. sms8198 features ? designed to operate with the philips trimedia processor coordinating the system reset function and providing the processor?s configuration memory multiple v trip thresholds - no external components required guaranteed reset assertion to v cc -1v reset is an i/o - allows system reset clean up - provides a de-bounced manual reset func- tion industry standard 2-wire serial interface hardware write lockout function high reliability - endurance: 100,000 write cycles - data retention: 100 years philips trimedia? processor companion supervisor with a 16k-bit 2-wire serial memory overview the sms8198 is a precision supervisory circuit designed specifically as a companion chip for the philips trimedia processor family. the sms8198 monitors the power supply and holds the system in reset whenever v cc is below the v trip threshold. in addition to the supervisory function, the sms8198 has 16k-bits of nonvolatile memory that is used by the trimedia processor as the boot memory. the sms8198 provides 16k-bits of memory that is acces- sible through the industry standard 2-wire serial interface. by integrating a precision supervisory circuit and the hardware wp input, the sms8198 becomes the perfect companion chip for the philips trimedia processor family. its functions are integral to the boot hardware operation of the trimedia processors. block diagram + ? gnd v cc 8 4 tri_reset# 2 v trip reset control wp 7 1.26v scl 6 sda 5 2036 t bd 2.0 write control nonvolatile memory array programmable reset pulse generator
2 sms8198 2036 5.0 4/18/00 sms8198 tr i media processor sda system boot block scl tri_reset# vcr/monitor audio local reset audio camera tri_reset# pci_reset# pci bus wp 10k 4.7k 4.7k 4.7k peripheral peripheral 2036 ill16.0 figure 1. typical implementation of the sms8198 and trimedia processor the boot hardware operation begins with the assertion of the reset signal tri_reset#. the tri_reset# output from the sms8198 is guaranteed to be valid at v cc -1.0v. the reset output is asserted whenever v cc is less than the v trip threshold and will remain asserted after v cc is >v trip for the duration of t purst . whenever the tri_reset# is active the memory will be write protected. in addition to the reset write protection feature, pin 7 can be tied to a pull-up to disable the write function of the memory. this effectively turns the memory array into an inexpensive boot rom. after reset is de-asserted, only the system boot block is allowed to operate. at this point the trimedia processor takes over and begins to download data from the memory array into its system boot block. the data downloaded contains configuration data to set up the trimedia proces- sor and to load special id information into the pci configu- ration space register. the id information is published in the pci configuration register to provide the 16 bit sub- system id and subsystem vendor id. it should be noted that both the threshold and the t purst pulse width are programmable. not only does this provide maximum flexibility to the designer, but, as the processor operating voltage levels migrate downwards, the sms8198 can be programmed to following this downward trend. the values can be selected from the ordering information table and the devices specified as standard off-the-shelf items.
3 2036 5.0 4/18/00 sms8198 figure 2. reset output timing symbol parameter part no. suffix min. typ. max. unit v trip reset trip point a (or) blank 4.250 4.375 4.5 v b 4.50 4.625 4.75 v 2.7 2.55 2.65 2.75 v t purst reset timeout 200 ms t rpd v trip to reset output delay 5 s v rvalid reset output valid to v cc min. guarantee 1 v t glitch glitch reject pulse width note 1 30 ns v olrs reset output low voltage i ol = 1ma 0.4 v v ohrs reset high voltage output i oh = 800a reset circuit ac and dc electrical characteristics t a = -40 c to +85 c v cc v rvalid v trip t purst 2036 t fig02 2.0 t glitch t rpd t purst t rpd tri_reset#
4 sms8198 2036 5.0 4/18/00 tri_reset# - is an active low open drain output. it is driven low whenever v cc is below v trip . tri_reset# is also an input and can be used to debounce a switch input or perform signal conditioning. the tri_reset# pin does have an internal pull-up and should be left uncon- nected if the signal is not used in the system. however, when the pin is tied to a system tri_reset# line an external pull-up resistor should be employed. write protect (wp) - all write operations can be disabled by maintaining wp > v ih . no connects (nc) - the no connect inputs are unused by the sms8198; however, to insure proper operation they can be unconnected or tied to ground. they must not be tied to v cc . endurance and data retention the sms8198 is designed for applications requiring up to 100,000 erase/write cycles and unlimited read cycles. it provides 100 years of secure data retention, with or without power applied, after the execution of 100,000 erase/write cycles. reset controller description the device provides a precise reset output to a microcontroller and it ? s associated circuitry ensuring cor- rect system operation during power-up/down conditions and brownout situations. the output is open drain, allow- ing control of the reset function by multiple devices. during power-up the reset output remains in a fixed active state until v cc passes through the reset threshold and remains above the threshold for t purst . the reset output is valid whenever v cc is equal to or greater than 1v. if v cc falls below the threshold for more than t glitch the device will immediately generate a reset and drive the output. the reset pin is an i/o; therefore, forcing the pin to the active state can also manually reset the device. because the i/o needs to be an open drain, the internal timer can only be triggered by the leading edge of the input. the resulting reset output will either be t purst , or the externally applied reset signal, whichever is longer. this can provide an affective debounce or reset signal extender solution. pin descriptions serial clock (scl) - the scl input is used to clock data into and out of the device. in the write mode, data must remain stable while scl is high. in the read mode, data is clocked out on the falling edge of scl. serial data (sda) - the sda pin is a bidirectional pin used to transfer data into and out of the device. data may change only when scl is low, except start and stop conditions. it is an open-drain output and may be wire- ored with any number of open-drain or open-collector outputs. pin names sda serial data i/o scl serial clock input tri_reset# reset output gnd ground v cc supply voltage wp write protect nc no connect pin configurations nc tri_reset# nc gnd v cc wp scl sda 1 2 3 4 8 7 6 5 8-pin soic 2036 t pcon 2.0
5 2036 5.0 4/18/00 sms8198 figure 3. input data protocol data must remain stable while clock is high. data must remain stable while clock is high. change of data allowed scl sda in t hd:dat t su:dat t hd:dat 2036 ill4.0 figure 4. acknowledge response from receiver scl from master data output from transmitter data output from receiver start condition acknowledge t aa t aa 1 8 9 2036 ill6.0
6 sms8198 2036 5.0 4/18/00 characteristics of the i 2 c bus general description the i 2 c bus was designed for two-way, two-line serial communication between different integrated circuits. the two lines are: a serial data line (sda), and a serial clock line (scl). the sda line must be connected to a positive supply by a pull-up resistor, located somewhere on the bus. data transfer between devices may be initiated with a start condition only when scl and sda are high (bus is not busy). input data protocol one data bit is transferred during each clock pulse. the data on the sda line must remain stable during clock high time, because changes on the data line while scl is high will be interpreted as start or stop condition (see figure 2). start and stop conditions when both the data and clock lines are high, the bus is said to be not busy. a high-to-low transition on the data line, while the clock is high, is defined as the ? start ? condition. a low-to-high transition on the data line, while the clock is high, is defined as the ? stop ? condi- tion (see figure 3). device operation the sms8198 is a 16,384-bit serial e 2 prom. the device supports the i 2 c bidirectional data transmission protocol. the protocol defines any device that sends data onto the bus as a ? transmitter ? and any device which receives data as a ? receiver. ? the device controlling data transmission is called the ? master ? and the controlled device is called the ? slave. ? in all cases, the sms8198 will be a ? slave ? device, since it never initiates any data transfers. acknowledge (ack) acknowledge is a software convention used to indicate successful data transfers. the transmitting device, either the master or the slave, will release the bus after transmit- figure 5. slave address byte ting eight bits. during the ninth clock cycle, the receiver will pull the sda line low to acknowledge that it received the eight bits of data (see figure 4). the sms8198 will respond with an acknowledge after recognition of a start condition and its slave address byte. if both the device and a write operation are selected, the sms8198 will respond with an acknowledge after the receipt of each subsequent 8-bit word. in the read mode, the sms8198 transmits eight bits of data, then releases the sda line, and monitors the line for an acknowledge signal. if an acknowledge is detected, and no stop condition is generated by the master, the sms8198 will continue to transmit data. if an acknowledge is not detected, the sms8198 will terminate further data transmissions and awaits a stop condition before returning to the standby power mode. device addressing following a start condition the master must output the address of the slave it is accessing. the most significant four bits of the slave address are the device type identifier (see figure 5). for the sms8198 this is fixed as 1010 bin . word address the next three bits of the slave address are an extension of the array ? s address and are concatenated with the eight bits of address in the word address field, providing direct access to the 2,048 x 8 array. read/write bit the last bit of the data stream defines the operation to be performed. when set to ? 1, ? a read operation is selected; when set to ? 0, ? a write operation is selected. 1 0 1 0 a10 a9 a8 r/w device identifier high order word address 2036 ill7.0
7 2036 5.0 4/18/00 sms8198 figure 6. page/byte write mode write operations the sms8198 allows two types of write operations: byte write and page write. the byte write operation writes a single byte during the nonvolatile write period (t wr ). the page write operation allows up to 16 bytes in the same page to be written during t wr . byte write after the slave address is sent (to identify the slave device, specify high order word address and a read or write operation), a second byte is transmitted which contains the low 8 bit addresses of any one of the 2,048 words in the array. upon receipt of the word address, the sms8198 re- sponds with an acknowledge. after receiving the next byte of data, it again responds with an acknowledge. the master then terminates the transfer by generating a stop condition, at which time the sms8198 begins the internal write cycle. while the internal write cycle is in progress, the sms8198 inputs are disabled, and the device will not respond to any requests from the master. refer to figure 6 for the address, acknowledge and data transfer sequence. page write the sms8198 is capable of a 16-byte page write opera- tion. it is initiated in the same manner as the byte-write operation, but instead of terminating the write cycle after the first data word, the master can transmit up to 15 more words of data. after the receipt of each word, the sms8198 will respond with an acknowledge. the sms8198 automatically increments the address for subsequent data words. after the receipt of each word, the four low order address bits are internally incremented by one. the high order five bits of the address byte remain constant. should the master transmit more than sixteen words, prior to generating the stop condition, the ad- dress counter will ? roll over, ? and the previously written data will be overwritten. as with the byte-write operation, all inputs are disabled during the internal write cycle. refer to figure 6 for the address, acknowledge and data transfer sequence. d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 d 7 d 5 d 6 d 4 d 0 d 3 d 2 d 1 s t a r t word address data byte n data byte n+15 s t o p a c k acknowledges transmitted from sms8198 to master receiver slave address device type address read/write 0= write a10,a9,a8 sda bus activity a c k a c k master sends read request to slave master writes word address to slave 1 0 1 0 0 data byte n+1 a c k master writes data to slave master transmitter to slave receiver slave transmitter to master receiver slave transmitter to master receiver master transmitter to slave receiver master transmitter to slave receiver shading denotes sms8198 sda output active master transmitter to slave receiver slave transmitter to master receiver slave transmitter to master receiver master transmitter to slave receiver slave transmitter to master receiver master writes data to slave master writes data to slave acknowledges transmitted from sms8198 to master receiver if single byte-write only, stop bit issued here. a 10 a 9 r w a c k a 8 2036 ill8.0
8 sms8198 2036 5.0 4/18/00 figure 8. current address byte read mode figure 7. acknowledge polling acknowledge polling when the sms8198 is performing an internal write operation, it will ignore any new start conditions. since the device will only return an acknowledge after it accepts the start, the part can be continuously queried until an acknowledge is issued, indicating that the internal write cycle is complete. to poll the device, give it a start condition, followed by a slave address for a write operation (see figure 7). read operations read operations are initiated with the r/w bit of the identification field set to ? 1. ? there are four different read options: 1. current address byte read 2. random address byte read 3. current address sequential read 4. random address sequential read current address byte read the sms8198 contains an internal address counter which maintains the address of the last word accessed, incremented by one. if the last address accessed (either a read or write) was to address location n, the next read operation would access data from address location n+1 and increment the current address pointer. when the sms8198 receives the slave address field with the r/w bit set to ? 1, ? it issues an acknowledge and transmits the 8-bit word stored at address location n+1. the current address byte read operation only accesses a single byte of data. the master does not acknowledge the transfer, but does generate a stop condition. at this point, the sms8198 discontinues data transmission. see fig- ure 8 for the address acknowledge and data transfer sequence. issue start internal write cycle in progress; begin ack polling issue slave address and r/w = 0 ack returned? next operation a write? issue byte address proceed with write issue stop await next command issue stop no no yes (internal write cycle is completed) yes 2036 ill9.0 s t a r t s t o p slave address device type address read/write 1= read a10,a9,a8 sda bus activity d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 master sends read request to slave slave sends data to master master transmitter to slave receiver slave transmitter to master receiver 1 1 1 00 1 lack of ack (low) from master determines last data byte to be read 1 shading denotes sms8198 sda output active a 9 a 10 r w a c k a 8 data byte 2036 ill10.0
9 2036 5.0 4/18/00 sms8198 figure 9. random address byte read mode random address byte read random address read operations allow the master to access any memory location in a random fashion. this operation involves a two-step process. first, the master issues a write command which includes the start condi- tion and the slave address field (with the r/w bit set to write) followed by the address of the word it is to read. this procedure sets the internal address counter of the sms8198 to the desired address. after the word address acknowledge is received by the master, the master immediately reissues a start condition followed by another slave address field with the r/w bit set to read. the sms8198 will respond with an acknowl- edge and then transmit the 8-data bits stored at the addressed location. at this point, the master does not acknowledge the transmission but does generate the stop condition. the sms8198 discontinues data transmission and reverts to its standby power mode. see figure 9 for the address, acknowledge and data transfer sequence. d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 s t a r t word address s t o p a c k slave address slave address device type address read/write 0= write device type address a10,a9,a8 a10,a9,a8 sda bus activity s t a r t read/write 1= read a c k a c k master sends read request to slave master writes word address to slave master requests data from slave slave sends data to master 1010 1010 1 0 a 10 a 9 r w a 8 a 9 r w a 10 a 8 lack of ack (low) from master determines last data byte to be read 1 slave transmitter to master receiver slave transmitter to master receiver shading denotes sms8198 sda output active slave transmitter to master receiver master transmitter to slave receiver master transmitter to slave receiver master transmitter to slave receiver slave transmitter to master receiver data byte 2036 ill11.0
10 sms8198 2036 5.0 4/18/00 sequential read sequential reads can be initiated as either a current address read or random access read. the first word is transmitted as with the other byte read modes (current address byte read or random address byte read); however, the master now responds with an acknowledge, indicating that it requires additional data from the sms8198. the sms8198 continues to output data for each acknowledge received. the master terminates the sequential read operation by not responding with an acknowledge, and issues a stop conditions. during a sequential read operation, the internal address counter is automatically incremented with each acknowl- edge signal. for read operations, all address bits are incremented, allowing the entire array to be read using a single read command. after a count of the last memory address, the address counter will ? roll-over ? and the memory will continue to output data. see figure 10 for the address, acknowledge and data transfer sequence. figure 10. sequential read operation (starting with a random address read) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 shading denotes sms8198 sda output active s t a r t word address s t o p a c k acknowledges from sms8198 slave address slave address device type address read/write 0= write device type address a10,a9,a8 a10,a9,a80 sda bus activity s t a r t read/write 1= read a 9 r w a 10 acknowledge from master receiver a c k a c k a c k master sends read request to slave master writes word address to slave master requests data from slave slave sends data to master slave transmitter to master receiver slave transmitter to master receiver master transmitter to slave receiver 1010 1010 1 0 slave sends data to master a 10 a 9 r w a 8 a 8 lack of ack (low) determines last data byte to be read 1 lack of acknowledge from master receiver slave transmitter to master receiver master transmitter to slave receiver master transmitter to slave receiver master transmitter to slave receiver slave transmitter to master receiver slave transmitter to master receiver last data byte first data byte 2036 ill12.0
11 2036 5.0 4/18/00 sms8198 absolute maximum ratings temperature under bias ......................................................................................................... ...... -40 c to +85 c storage temperature ............................................................................................................ ......... -65 c to +125 c soldering temperature (less than 10 seconds) ................................................................................... ........... 300 c supply voltage ................................................................................................................. .......................... 0 to 6.5v voltage on any pin ............................................................................................................. ......... -0.3v to v cc +0.3v esd voltage (jedec method) ..................................................................................................... ................. 2,000v note: these are stress ratings only. appropriate conditions for operating these devices are given elsewhere in this specificati on. stresses beyond those listed here may permanently damage the part. prolonged exposure to maximum ratings may affect device reliability. dc electrical characteristics sms8198, t a = -40 c to +85 c, v cc = 2.7v to 5.5v symbol parameter conditions min max units scl = cmos levels @ 100khz v cc =5.5v 3 ma i cc supply current (cmos) sda = open all other inputs = gnd or v cc v cc =3.3v 2 ma i sb standby current (cmos) scl = sda = v cc v cc =5.5v 50 a all other inputs = gnd i li input leakage v in = 0 to v cc 10 a i lo output leakage v out = 0 to v cc 10 a v il input low voltage s0, s1, s2, scl, sda, reset 0.3xv cc v v ih input high voltage s0, s1, s2, scl, sda 0.7xv cc v v ol output low voltage i ol = 3ma 0.4 v v rol reset low output v cc = 1.0v, i ol = 100a 0.3 v v cc = 2.7v, i ol = 400a 0.3 v v cc = 4.5v, i ol = 1ma 0.4 v v cc =3.3v 25 a 2036 pgm t1.1 l o b m y sr e t e m a r a ps n o i t i d n o c v 5 . 4 o t v 7 . 2v 5 . 5 o t v 5 . 4 s t i n u . n i m. x a m. n i m. x a m f l c s y c n e u q e r f k c o l c l c s00 0 10 0 4z h k t w o l d o i r e p w o l k c o l c7 . 43 . 1s t h g i h d o i r e p h g i h k c o l c0 . 46 . 0s t f u b e m i t e e r f s u bn o i s s i m s n a r t w e n e r o f e b7 . 43 . 1s t a t s : u s e m i t p u t e s n o i t i d n o c t r a t s7 . 46 . 0s t a t s : d h e m i t d l o h n o i t i d n o c t r a t s0 . 46 . 0s t o t s : u s e m i t p u t e s n o i t i d n o c p o t s7 . 46 . 0s t a a t u p t u o o t k c o l cd i l a v t u o a t a d a d s o t w o l l c s3 . 05 . 32 . 09 . 0s t h d e m i t d l o h t u o a t a de g n a h c t u o a t a d a d s o t w o l l c s3 . 02 . 0s t r e m i t e s i r a d s d n a l c s 13 . 0s t f e m i t l l a f a d s d n a l c s 3 . 03 . 0s t t a d : u s e m i t p u t e s n i a t a d0 5 20 0 1s n t t a d : d h e m i t d l o h n i a t a d00s n t i l c s @ h t d i w e k i p s e s i o n s t u p n i a d s & t n a t s n o c e m i t n o i s e r p p u s e s i o n0 0 10 0 1s n t r w e m i t e l c y c e t i r w 0 10 1s m ac electrical characteristics sms8198, t a = -40 c to +85 c, v cc = 2.7v to 5.5v
12 sms8198 2036 5.0 4/18/00 figure 11. bus timing capacitance t a = 25 c, f = 100khz symbol parameter max units c in input capacitance 5 pf c out output capacitance 8 pf 2036 pgm t3.0 t f t r t low t high t hd:sda t su:sda t buf t dh t hd:dat t su:dat t su:sto scl sda in sda out t aa 2047 fig07 1.0
13 2036 5.0 4/18/00 sms8198 ordering information v trip threshold a or blank = 4.5v b = 4.75v 2.7 = 2.7v sms8198 s a base part number package s = 8 lead soic 2036 tree 2.0
14 sms8198 2036 5.0 4/18/00 notice summit microelectronics, inc. reserves the right to make changes to the products contained in this publication in order to impr ove design, performance or reliability. summit microelectronics, inc. assumes no responsibility for the use of any circuits describ ed herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user ? s specific application. while the information in this publication has been carefully checked, summit microelectronics, inc. shall not be liable for any damages arising as a result of any error or omission. summit microelectronics, inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless summit microelectronics, inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all su ch risks; and (c) potential liability of summit microelectronics, inc. is adequately protected under the circumstances. i 2 c is a trademark of philips corporation. ? copyright 2000 summit microelectronics, inc. .228 (5.80) .244 (6.20) .016 (.40) .035 (.90) .020 (.50) .010 (.25) x45 .0192 (.49) .0138 (.35) .061 (1.75) .053 (1.35) .0098 (.25) .004 (.127) .05 (1.27) typ. .275 (6.99) typ. .030 (.762) typ. 8 places .050 (1.27) typ. .050 (1.270) typ. 8 places .157 (4.00) .150 (3.80) .196 (5.00) 1 .189 (4.80) footprint 8pn jedec soic ill.2 8 pin soic (type s) package jedec (150 mil body width)

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